The information displayed on cathode ray tube ("CRT") video display devices, used with equipment such as personal computers, is driven by analog video signals. As shown in FIG. 1, a typical analog video signal is a composite signal having analog data combined with other sweep and synchronization signals. Synchronization signals are embedded within the composite video signal at predetermined voltage levels, which are recognized as synch levels. The synch level of a video signal is used by the CRT interface to cue the electron beam of the CRT to change either a scan line or a frame when displaying information. When the sync level cues the electron beam to start at the next scan line, it is called a horizontal sync ("H-sync").
With the cost of digital display devices, such as liquid crystal displays ("LCD") or thin film transistor displays dramatically decreasing in recent years, CRT's are being replaced in the computer industry by the use of flat panel displays ("FPD") on personal computers and by the increased popularity of notebook computers, such as the Hitachi Visionbook products.
Digital video displays are driven by digital pixel data instead of analog video signals. Thus, analog video signals generated by the host computer must be converted into the digital domain by an analog to digital converter in order to be used by digital display devices. In the conversion of display information from analog to digital pixel data, a dot (pixel) clock signal in the FPD must be synchronized with the original dot clock signal which was used to create the analog video signals.
Unfortunately, the CRT interface of a typical personal computer does not include a dot clock signal, which would be used by the FPD during the generation of display data. Therefore, interface circuitry for LCD and other FPD devices must use a PLL circuit or other synchronizing circuits to regenerate the dot clock signal from the H-sync transmitted by the host computer (see FIG. 2).
For example, U.S. Pat. No. 4,791,488, issued on Dec. 13, 1996, provides a method for accurate dot clock phase matching to a composite video signal. This is achieved by synchronizing the horizontal sync pulse to the dot clock and providing matched propagation delays up to the analog to digital conversion circuitry. The dot clock timing, however, is referenced only to the start of the horizontal sync signal. This can lead to timing jitters due to H-sync signal tolerances, as described below. U.S. Pat. No. 4,998,169, issued on Mar. 5, 1991, discloses a circuit for the flat panel dot clock regeneration without using a phase locked loop. In this disclosure, the horizontal drive is used to reset counters at the beginning of the horizontal line scan. In U.S. Pat. No. 4,864,399, issued on Sep. 5, 1989, a circuit is provided to correct chroma demodulation for digital TV receivers In the circuit disclosed, the A/D clock phase is updated at the start of each horizontal drive.
Under current Video Electronic Standards Association ("VESA") timing standards, the H-sync time period has a prescribed number of clock pulses for each of the different image resolutions. For example, VESA standards set the extended graphics array ("XGA") mode line period at 1344 clock pulses, for a 60 Hz refresh rate. One clock period is therefore 1/1344 or 0.075% of the line length. VESA standards further provide that the tolerance for the dot clock used by the random access memory digital to analog converter ("RAMDAC") for converting display data into analog signal transitions is less than + or -0.5% from the nominal values, a deviation that is several times larger than the 0.075% dot clock width of the horizontal period. Therefore, synchronizing the H-sync signal to video signal transitions alone cannot be used to accurately recover the dot clock frequency. The line period will have the number of clock pulses which is either larger or smaller than the standard requires, depending on the frequency tolerance. In XGA mode, for example, the number of clock pulses may deviate up to .+-.6 clock periods.
Signal transitions are, however, synchronous with and in phase with the dot clock at the RAMDAC output of the host computer. In addition, the H-sync signal is synchronous with the dot clock signals. Unfortunately, the leading edge timing of the H-sync signal relative to signal transitions is not defined by the VESA standards (or other applicable standards). The lack of specific parameters for the H-sync signal timing produces a regenerated dot clock signal based on the H-sync signal that, for flat panel displays, doesn't always synchronize in phase with video signals. This results in FPD image details that exhibit a high amount of timing jitters.
Accordingly, what is needed is a device and method for synchronizing the regenerated dot clock signal with the H-sync signals and voltage transitions of analog video signals, that overcomes the deficiencies and inadequacies of the prior art devices while complying with current timing standards.
It is, therefore, an object of the present invention to provide an apparatus and method for regenerating an accurate dot clock period from the H-sync signal and for recovering an accurate dot clock phase from the signal transitions of the red, green and blue analog video signals.
It is still another object of the present invention to accomplish to above-stated object by utilizing a phase lock loop method and apparatus which is simple in design and use, and efficient to manufacture.
The foregoing objects and advantages of the invention are illustrative of those which can be achieved by the present invention and are not intended to be exhaustive or limiting of the possible advantages which can be realized. Thus, these and other objects and advantages of the invention will be apparent from the description herein or can be learned from practicing the invention, both as embodied herein or as modified in view of any variation which may be apparent to those skilled in the art. Accordingly, the present invention resides in the novel methods, arrangements, combinations and improvements herein shown and described.